FIG. 20 is a cross-sectional view illustrating a prior art pin photodiode (hereinafter referred to as pin PD) provided with an InGaAs light absorbing layer according to the prior art. In FIG. 20, reference numeral 1 designates a high dopant concentration n type (hereinafter referred to as n.sup.+ -) InP substrate including an n type dopant impurity, such as S (sulfur) or Si (silicon), in a concentration of 1.times.10.sup.18 cm.sup.-3 and having a thickness of 200 .mu.m. Reference numeral 2 designates an n type (hereinafter referred to as n-) InP buffer layer including an n type dopant impurity in a concentration of 1.times.10.sup.17 cm.sup.-3 and having a thickness of about 1 .mu.m. Reference numeral 3 designates a low dopant concentration n type (hereinafter referred to as n.sup.- -) InGaAs light absorbing layer including an n type dopant impurity in a concentration of 1.times.10.sup.15 cm.sup.-3 and having a thickness of about 3 .mu.m. Reference numeral 4 designates an n.sup.- -InP window layer including an n type dopant impurity in a concentration of 1.times.10.sup.14 .about.1.times.10.sup.15 cm.sup.-3 and having a thickness of about 2 .mu.m. Reference numeral 5 designates a p type region having a circular surface formed by Zn diffusion with its diameter of about 60 .mu.m and having a dopant concentration of 1.times.10.sup.17 cm.sup.-3 .about.1.times.10.sup.20 cm.sup.-3. Reference numeral 6 designates a p type (hereinafter referred to as p-) InGaAs contact layer including a p type dopant impurity to a concentration of 1.times.10.sup.19 cm.sup.-3 and having a thickness of about 0.2 .mu.m. The contact layer has an annular surface with an internal diameter of about 50 .mu.m and a width of about 5 .mu.m, and the center of the annular surface is positioned at the center of the circular p type region. Reference numeral 7 designates a reflection preventing film (passivation film) comprising such as SiN and having a thickness of about 1500 .ANG., disposed on the n.sup.- InP window layer 4 other than the region where the contact layer 6 is formed. Reference numeral 8 designates a p side electrode disposed on the contact layer 6, and a portion thereof extending onto a region where the contact layer 6 is not present. The extended portion provides a bonding pad region B which is used for wire bonding. Reference numeral 9 designates an insulating film such as SiO.sub.2 having a thickness of about 4000 .ANG. and disposed between the bonding pad region B of the p side electrode 8 and the reflection preventing film 7. Reference numeral 10 designates an n side electrode provided on the rear surface of the substrate 1. In addition, character L denotes a distance between the outer contour of the InGaAs contact layer 6 and the outer contour of the Zn diffusion region 5 at the surface of the window layer 4. Reference numeral 5a designates a light responsive region.
A description is given of the operation of the prior art pin PD. First of all, when a reverse bias current flows so that the p side electrode 8 becomes minus and the n side electrode 10 becomes plus, a depletion layer is formed from the pn junction plane between the p type region 5 and the n.sup.- -InGaAs light absorbing layer 3 toward the direction of the n.sup.+ -InP substrate 1. Then, when the light is applied at the front surface of the n.sup.- -InP window layer 4 to the n.sup.- -InGaAs light absorbing layer 3 in the depletion layer, carriers are excited in the n.sup.- -InGaAs light absorbing layer 3, and a photoelectric current flows in accordance with the quantity of incident light.
The prior art InGaAs-pin PD has two problems because the window layer 4 comprises n.sup.- -InP. First, a bonding pad capacitance is produced between the bonding pad region B of the electrode 8 and the lower surface of the depletion layer that is generated at the upper portion of the window layer 4 when the reverse bias is applied, and this capacitance is determined by the sum of the capacitance of the insulating film, such as the SiN reflection preventing film 7 formed on the surface of the window layer 4, and the capacitance of the depletion layer. Usually in the PD, since a reduction in the capacitance of the device enhances the high-speed response of the device, the device has an insulating film 9 such as SiO.sub.2 between the window layer 4 and the bonding pad region B of the electrode 8, which insulating film 9 is as thick as possible, to reduce the bonding pad capacitance. However, since there is a limitation in providing such an insulating film 9, it is impossible to reduce the bonding pad capacitance easily.
Second, in order to reduce the capacitance of the pin PD, the diffusion radius of the p type region 5 forming the pn junction capacitance with the n type semiconductor layer is made closer to the light responsive radius of the light responsive region 5a, and the pn junction area is made small. However, when the distance L is shortened, the dark current increases with an increase in the leakage current flowing at the interface between the reflection preventing film 7 and the window layer 4 through the contact layer 6 from the p side electrode 8. Therefore, it is impossible to minimize the diffusion radius of the p type region 5, and it is impossible to reduce the pn junction capacitance. Because of these two problems in the prior art pin PD, there is a limitation in reducing the device capacitance, and it is difficult to realize high-speed operation of the device.
FIG. 21 is a cross-sectional view illustrating an avalanche photodiode (hereinafter referred to as APD) provided with the InGaAs light absorbing layer according to the prior art. In FIG. 21, the same reference numerals as in FIG. 20 designate the same or corresponding parts. Reference numeral 25 designates an n-type hole accumulation prevention layer comprising n type InGaAsP including an n type dopant impurity in a concentration of 1.times.10.sup.15 cm.sup.-3 and having a thickness of about 0.2 .mu.m, and disposed so that the holes generated in the light absorbing layer 3 easily move toward the p type region 5. Reference numeral 11 designates an n-InP multiplication layer including an n type dopant impurity in a concentration of 2.times.10.sup.16 cm.sup.-3 and having a thickness of about 1 .mu.m. Reference numeral 14 designates an n.sup.- -InP window layer including an n type dopant impurity in, a concentration of 1.times.10.sup.15 cm.sup.-3 and having a thickness of about 1 .mu.m. Reference numeral 24 designates a guard ring region formed by ion implantation of Be.
A description is given of the operation of the prior art APD. First of all, when a reverse bias current flows so that the p side electrode 8 becomes minus and the n side electrode 10 becomes plus, a depletion layer having a depth reaching the n.sup.- -InGaAs light absorbing layer 3 is formed from the pn junction plane between the p type region 5 and the n-InP multiplication layer 11 toward the direction of the n.sup.+ -InP substrate 1. Then, when light is applied from the surface of the n.sup.- -InP window layer 4 to the n.sup.- -InGaAs light absorbing layer 3 in the depletion layer, the carriers are excited by the n.sup.- -InGaAs light absorbing layer 3, and the carriers are multiplied by the avalanche phenomenon, thereby producing a photoelectric current in accordance with the quantity of the incident light.
The p type region formed by diffusion of Zn atoms usually forms a stepwise pn junction, at the interface between the multiplication layer 11 and the p type region 5 and at the interface between the n.sup.- -InP window layer 14 and the p type region 5. At the edge part, i.e., the sidewall, of the p type region 5, the electric field is likely to be concentrated because the pn junction interface curved, and edge breakdown is likely to arise. In order to avoid the edge breakdown, in the usual APD, a guard ring region 24 having an inclined pn junction formed by a combination of Be ion implantation and annealing is provided in the vicinity of the edge part. That is, edge breakdown can be prevented by providing the inclined pn junction, which is unlikely to breakdown in place of the stepwise pn junction which is likely to breakdown.
However, since the annealing temperature in producing the guard ring region 24 is extreme, 600.degree..about.800.degree. C., dissociations and crystalline defects occur and increase the dark current, and the characteristics of the semiconductor element are degraded. Therefore, it is necessary to prevent dissociation that increases the dark current.
In addition, in the prior art APD, as in the above-described pin PD, since the bonding pad capacitance is not reduced, high-speed operation of the device is not realized.
FIG. 22 is a cross-sectional view illustrating a laser diode (hereinafter refereed to as LD) according to the prior art. In FIG. 22, reference numeral 51 designates an n.sup.+ -InP substrate including an n type dopant impurity, such as S or Si, in a concentration of 5.times.10.sup.18 cm.sup.-3. Reference numeral 52 designates an n-InP lower cladding layer including an n type dopant impurity in a concentration of 1.times.10.sup.18 cm.sup.-3. Reference numeral 53 designates a p-InP current blocking layer including a p type dopant impurity in a concentration of 1.times.10.sup.18 cm.sup.-3. Reference numeral 54 designates an n-InP current blocking layer including an n type dopant impurity in a concentration of 1.times.10.sup.17 cm.sup.-3. Reference numeral 55a designates a first p-InP upper cladding layer including a p type dopant impurity in a concentration of 1.times.10.sup.18 cm.sup.-3. Reference numeral 55b designates a second p-InP upper cladding layer including a p type dopant impurity in a concentration of 1.times.10.sup.18 cm.sup.-3. Reference numeral 56 designates an undoped InGaAs active layer. Reference numeral 57 designates an insulating film such as SiN. Reference numeral 58 designates a p side electrode, and reference numeral 50 designates an n side electrode.
Subsequently, a description is given of the method of fabricating the prior art LD. First of all, the lower cladding layer 52, the undoped InGaAs active layer 56, and the first upper cladding layer 55b are successively epitaxially grown on the substrate 51 by MOCVD as the first epitaxial growth step.
Next, a stripe-shaped insulating film (not shown) is formed on the first upper cladding layer 55b, and using this film as a mask, the etching is selectively performed to reach the lower cladding layer 52 from the surface of the first upper cladding layer 55b, to form a stripe-shaped mesa structure.
Further, using the stripe-shaped insulating film as a mask, the p-InP current blocking layers 53 and the n-InP current blocking layers 54 are successively epitaxially grown so as to bury the mesa structure at opposite sides thereof by MOCVD as the second epitaxial growth step. Then, after the removal of the insulating film, the second upper cladding layer 55b is formed on the mesa structure and the n-InP blocking layers 54 as the third epitaxial growth step. Further, an insulating film 57 having an aperture above the mesa structure is formed on the second upper cladding layer 55b, and the p side electrode 58 is formed on the second upper cladding layer 55b in the aperture and on the insulating film 57, and an n side electrode 50 is formed on the rear surface of the substrate 51, thereby producing a laser diode as shown in FIG. 22.
A description is given of the prior art LD. When a current flows so that the p side electrode 58 becomes plus and the n side electrode 50 becomes minus, the carriers injected from the respective electrodes reach the active layer 56 in the mesa structure, light emitting recombination of carriers occurs, the light is guided along the active layer 56, and the light is emitted as a laser beam. As for the carriers injected from the p side electrode 58 and the n side electrode 50, since the n-InP lower cladding layer 52, the p-InP current blocking layer 53, the n-InP current blocking layer 54, and the second p-InP upper cladding layer 55b are successively laminated to form a thyristor structure (pnpn structure), the carriers do not flow.
As described above, in the prior art LD, a mesa structure is formed as a structure confining the current, and the opposite sides of the mesa structure are buried by the p-InP current blocking layers 53 and the n-InP current blocking layers 54, and the second p-InP upper cladding layer 55b is disposed on the mesa structure and on the n-InP current blocking layers 54. However, in order to fabricate the LD having such a structure, it is necessary to perform three epitaxial growth processes, that is forming the mesa structure, burying the mesa structure, and forming the second p-InP upper cladding layer 55b. As a result, the fabricating processes become quite complicated, and the productivity is quite bad.
In the prior art semiconductor device such as a pin PD, since the window layer 4 comprises n.sup.- type InP, the bonding pad capacitance cannot be easily reduced, and there is a limitation in making the diffusion radius of light responsive region 5a of the p type region 5 causing a pn junction capacitance close to the radius of the light responsive region, whereby it is impossible to reduce the pn junction capacitance. As a result, it was difficult to realize the high-speed operation of the device.
In the prior art semiconductor device such as an APD, since the annealing temperature while forming the guard ring region 24 is extreme, 600.degree..about.800.degree. C., dissociations and crystalline defects occur and the dark current increases, whereby the characteristics of the semiconductor element are degraded. As a result, it is impossible to reduce the bonding pad capacitance, and it is difficult to realize high-speed operation of the device.
In addition, in the prior art semiconductor device such as an LD, since it is necessary to perform three epitaxial growth processes, that is forming the mesa structure, burying the mesa structure, and forming the second p-InP upper cladding layer 55b, the fabricating processes become quite complicated, and the productivity is quite bad.